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- 1 - in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device. preliminary description the lh28f320s3-l/s3h-l flash memories with smart 3 technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications, having high programming performance is achieved through highly-optimized page buffer operations. their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, simms and memory cards. their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the lh28f320s3-l/s3h-l offer three levels of protection : absolute protection with v pp at gnd, selective hardware block locking, or flexible software block locking. these alternatives give designers ultimate control of their code security needs. the lh28f320s3-l/s3h-l are conformed to the flash scalable command set (scs) and the common flash interface (cfi) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. features ? smart 3 technology C 2.7 v or 3.3 v v cc C 2.7 v, 3.3 v or 5 v v pp ? high speed write performance C two 32-byte page buffers C 2.7 s/byte write transfer rate ? common flash interface (cfi) C universal & upgradable interface ? scalable command set (scs) ? high performance read access time lh28f320s3-l11/s3h-l11 C 110 ns (3.30.3 v)/140 ns (2.7 to 3.6 v) lh28f320s3-l14/s3h-l14 C 140 ns (3.30.3 v)/160 ns (2.7 to 3.6 v) ? enhanced automated suspend options C write suspend to read C block erase suspend to write C block erase suspend to read ? enhanced data protection features C absolute protection with v pp = gnd C flexible block locking C erase/write lockout during power transitions ? sram-compatible write interface ? user-configurable x8 or x16 operation ? high-density symmetrically-blocked architecture C sixty-four 64 k-byte erasable blocks ? enhanced cycling capability C 100 000 block erase cycles C 6.4 million block erase cycles/chip ? low power management C deep power-down mode C automatic power saving mode decreases i cc in static mode ? automated write and erase C command user interface C status register ? etox tm * v nonvolatile flash technology ? packages C 56-pin ssop (ssop056-p-0600) C 80-ball csp (fbga080/064-p-0818) * etox is a trademark of intel corporation. lh28f320s3-l/s3h-l 32 m-bit (4 mb x 8/2 mb x 16) smart 3 flash memories (fast programming) lh28f320s3-l/s3h-l
preliminary lh28f320s3-l/s3h-l - 2 - pin connections 56-pin ssop (ssop056-p-0600) ce 0 # a 12 a 13 a 14 a 15 nc ce 1 # a 21 a 20 a 19 a 18 a 17 a 16 v cc gnd dq 6 dq 14 dq 7 dq 15 sts oe# we# wp# dq 13 dq 5 dq 12 dq 4 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 v pp rp# a 11 a 10 a 9 a 1 a 2 a 3 a 4 a 5 a 6 a 7 gnd a 8 v cc dq 9 dq 1 dq 8 dq 0 a 0 byte# nc nc dq 2 dq 10 dq 3 dq 11 gnd nc 1 a b c d e nc 2 nc 345 nc 6 nc 7 a 17 a 15 a 12 rp# a 9 a 20 8 9 10 11 12 13 14 15 16 17 18 19 20 a 18 v cc ce 0 # v pp a 8 f a 7 a 6 g nc nc nc nc nc a 4 a 21 a 19 a 14 a 13 a 11 a 10 a 5 a 3 nc ce 1 # a 16 nc nc gnd a 2 a 1 wp# we# dq 6 nc nc dq 9 nc nc oe# dq 15 dq 5 dq 12 dq 3 dq 10 dq 0 byte# sts dq 7 gnd v cc gnd v cc dq 8 a 0 nc dq 14 dq 13 dq 4 dq 11 dq 2 dq 1 nc nc nc nc nc nc nc nc nc h (fbga080/064-p-0818) 80-ball csp top view comparison table versions operating temperature dc characteristics v cc deep power-down current (max.) lh28f320s3-l 0 to +70?c 20 a LH28F320S3H-L C 40 to +85?c 25 a
preliminary lh28f320s3-l/s3h-l - 3 - block diagram output buffer input buffer i/o logic command user interface ce# we# rp# oe# identifier register status register data comparator y gating y decoder decoder x 64 64 k-byte blocks input buffer address latch address counter write state machine program/erase voltage switch sts gnd query rom register data wp# byte# multiplexer buffer page output multiplexer v cc v pp v cc a 0 -a 21 dq 0 -dq 15
preliminary lh28f320s3-l/s3h-l - 4 - pin description symbol type name and function address inputs : inputs for addresses during read and write operations. addresses are internally latched during a write cycle. a 0 : byte select address. not used in x16 mode (can be floated). a 1 -a 4 : column address. selects 1 of 16-bit lines. a 5 -a 15 : row address. selects 1 of 2 048-word lines. a 16 -a 21 : block address. data input/outputs : dq 0 -dq 7 : inputs data and commands during cui write cycles; outputs data during memory array, status register, query, and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. dq 8 -dq 15 : inputs data during cui write cycles in x16 mode; outputs data during memory array read cycles in x16 mode; not used for status register, query and identifier code read mode. data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode (byte# = v il ). data is internally latched during a write cycle. ce 0 #, ce 1 # input chip enable : activates the devices control logic, input buffers decoders, and sense amplifiers. either ce 0 # or ce 1 # v ih deselects the device and reduces power consumption to standby levels. both ce 0 # and ce 1 # must be v il to select the devices. rp# input reset/deep power-down : puts the device in deep power-down mode and resets internal automation. rp# v ih enables normal operation. when driven v il , rp# inhibits write operations which provide data protection during power transitions. exit from deep power-down sets the device to read array mode. oe# input output enable : gates the devices outputs during a read cycle. we# input write enable : controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. sts (ry/by#) : indicates the status of the internal wsm. when configured in level mode (default mode) , it acts as a ry/by# pin. when low, the wsm is performing an internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit configuration). sts high z indicates that the wsm is ready for new commands, block erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or the device is in deep power-down mode. for alternate configurations of the status pin, see the configuration command ( table 3 and section 4.14 ). wp# input write protect : master control for block locking. when v il , locked blocks can not be erased and programmed, and block lock-bits can not be set and reset. byte# input byte enable : byte# v il places device in x8 mode. all data are then input or output on dq 0-7 , and dq 8-15 float. byte# v ih places the device in x16 mode, and turns off the a 0 input buffer. block erase, full chip erase, (multi) word/byte write, block lock- bit configuration power supply : for erasing array blocks, writing bytes or configuring block lock-bits. with v pp v pplk , memory contents cannot be altered. block erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid v pp (see section 6.2.3 "dc characteristics" ) produce spurious results and should not be attempted. v cc supply device power supply : internal detection configures the device for 2.7 v or 3.3 v operation. to switch from one voltage to another, ramp v cc down to gnd and then ramp v cc to the new voltage. do not float any power pins. with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see section 6.2.3 "dc characteristics" ) produce spurious results and should not be attempted. gnd supply ground : do not float any ground pins. nc no connect : lead is not internal connected; recommend to be floated. dq 0 -dq 15 input/ output open sts drain output a 0 -a 21 input v pp supply
preliminary 1 introduction this datasheet contains lh28f320s3-l/s3h-l specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications. lh28f320s3-l/ s3h-l flash memories documentation also includes ordering information which is referenced in section 7. 1.1 product overview the lh28f320s3-l/s3h-l are high-performance 32 m-bit smart 3 flash memories organized as 4 mb x 8/2 mb x 16. the 4 mb of data is arranged in sixty-four 64 k-byte blocks which are individually erasable, lockable, and unlockable in-system. the memory map is shown in fig. 1 . smart 3 technology provides a choice of v cc and v pp combinations, as shown in table 1 , to meet system performance and power expectations. v pp at 2.7 v, 3.3 v and 5 v eliminates the need for a separate 12 v converter. in addition to flexible erase and program voltages, the dedicated v pp pin gives complete data protection when v pp v pplk . table 1 v cc and v pp voltage combinations offered by smart 3 technology internal v cc and v pp detection circuitry auto- matically configures the device for optimized read and write operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. a block erase operation erases one of the devices 64 k-byte blocks typically within 0.41 second (3.3 v v cc , 5 v v pp ) independent of other blocks. each block can be independently erased 100 000 times (6.4 million block erases per device). block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block. a word/byte write is performed in byte increments typically within 12.95 s (3.3 v v cc , 5 v v pp ). a multi word/byte write has high speed write performance of 2.7 s/byte (3.3 v v cc , 5 v v pp ). (multi) word/byte write suspend mode enables the system to read data from, or write data to any other flash memory array location. individual block locking uses a combination of bits and wp#, sixty-four block lock-bits, to lock and unlock blocks. block lock-bits gate block erase, full chip erase and (multi) word/byte write operations. block lock-bit configuration operations (set block lock-bit and clear block lock-bits commands) set and cleared block lock-bits. the status register indicates when the wsms block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished. the sts output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using sts minimizes both cpu overhead and system power consumption. sts pin can be configured to different states using the configuration command. the sts pin defaults to ry/by# operation. when low, sts indicates that the wsm is performing a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. sts high z indicates that the wsm is ready for a new command, block v cc voltage v pp voltage 2.7 v 2.7 v, 3.3 v, 5 v 3.3 v 3.3 v, 5 v lh28f320s3-l/s3h-l - 5 -
- 6 - preliminary lh28f320s3-l/s3h-l erase is suspended and (multi) word/byte write are inactive, (multi) word/byte write are suspended, or the device is in deep power-down mode. the other 3 alternate configurations are all pulse mode for use as a system interrupt. the access time is 110 ns or 140 ns (t avqv ) at the v cc supply voltage range of 3.0 to 3.6 v over the temperature range, 0 to +70c (lh28f320s3-l)/ C 40 to +85c (LH28F320S3H-L). at 2.7 to 3.6 v v cc , the access time is 140 ns or 160 ns. the automatic power saving (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i ccr current is 3 ma at 2.7 v and 3.3 v v cc . when either ce 0 # or ce 1 #, and rp# pins are at v cc , the i cc cmos standby mode is enabled. when the rp# pin is at gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phel ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared.
- 7 - preliminary lh28f320s3-l/s3h-l 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 1fffff 1f0000 1effff 1e0000 1dffff 1d0000 1cffff 1c0000 1bffff 1b0000 1affff 1a0000 19ffff 190000 18ffff 180000 17ffff 170000 16ffff 160000 15ffff 150000 14ffff 140000 13ffff 130000 12ffff 120000 11ffff 110000 10ffff 100000 0fffff 0f0000 0effff 0e0000 0dffff 0d0000 0cffff 0c0000 0bffff 0b0000 0affff 0a0000 09ffff 090000 08ffff 080000 07ffff 070000 06ffff 060000 05ffff 050000 04ffff 040000 03ffff 030000 02ffff 020000 01ffff 010000 00ffff 000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 3fffff 1f0000 3effff 3e0000 3dffff 3d0000 3cffff 3c0000 3bffff 3b0000 3affff 3a0000 39ffff 390000 38ffff 380000 37ffff 370000 36ffff 360000 35ffff 350000 34ffff 340000 33ffff 330000 32ffff 320000 31ffff 310000 30ffff 300000 2fffff 2f0000 2effff 2e0000 2dffff 2d0000 2cffff 2c0000 2bffff 2b0000 2affff 2a0000 29ffff 290000 28ffff 280000 27ffff 270000 26ffff 260000 25ffff 250000 24ffff 240000 23ffff 230000 22ffff 220000 21ffff 210000 20ffff 200000 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 fig. 1 memory map
- 8 - preliminary lh28f320s3-l/s3h-l 2 principles of operation the lh28f320s3-l/s3h-l flash memories include an on-chip wsm to manage block erase, full chip erase, (multi) word/byte write and block lock-bit configuration functions. it allows for : 100% ttl- level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see table 2.1 and table 2.2 "bus operations" ) , the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations. status register, query structure and identifier codes can be accessed through the cui independent of the v pp voltage. high voltage on v pp enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. all functions associated with altering memory contentsblock erase, full chip erase, (multi) word/byte write and block lock-bit configuration, status, query and identifier codesare accessed via the cui and verified through the status register. commands are written using standard micro- processor write timings. the cui contents serve as input to the wsm, which controls the block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latched during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, outputs query structure or outputs status register data. interface software that initiates and polls progress of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspended. write suspend allows system software to suspend a (multi) word/byte write to read data from any other flash memory array location. 2.1 data protection depending on the application, the system designer may choose to make the v pp power supply switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to v pph1/2/3 . the device accommodates either design practice and encourages optimization of the processor-memory interface. when v pp v pplk , memory contents cannot be altered. the cui, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to v pp . all write functions are disabled when v cc is below the write lockout voltage v lko or when rp# is at v il . the devices block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations.
- 9 - preliminary lh28f320s3-l/s3h-l 3 bus operation the local cpu reads and writes flash memory in- system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes, query structure, or status register independent of the v pp voltage. rp# must be at v ih . the first task is to write the appropriate read mode command (read array, read identifier codes, query or read status register) to the cui. upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. five control pins dictate the data flow in and out of the component : ce# (ce 0 #, ce 1 #) , oe#, we#, rp# and wp#. ce 0 #, ce 1 # and oe# must be driven active to obtain data at the outputs. ce 0 # and ce 1 # are the device selection control, and when active enables the selected memory device. oe# is the data output (dq 0 -dq 15 ) control and when active drives the selected memory data onto the i/o bus. we# and rp# must be at v ih . fig. 15 and fig. 16 illustrate a read cycle. 3.2 output disable with oe# at a logic-high level (v ih ) , the device outputs are disabled. output pins dq 0 -dq 15 are placed in a high-impedance state. 3.3 standby either ce 0 # or ce 1 # at a logic-high level (v ih ) places the device in standby mode which substantially reduces device power consumption. dq 0 -dq 15 outputs are placed in a high-impedance state independent of oe#. if deselected during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 deep power-down rp# at v il initiates the deep power-down mode. in read modes, rp#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. rp# must be held low for a minimum of 100 ns. time t phqv is required after return from power-down until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration modes, rp#-low will abort the operation. sts remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharps flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu.
- 10 - preliminary reserved for future implementation block 63 status code block 63 block 1 block 0 (blocks 2 through 62) reserved for future implementation reserved for future implementation block 1 status code reserved for future implementation reserved for future implementation block 0 status code device code manufacture code 3fffff 3f0006 3f0005 3f0004 3f0003 3f0000 3effff 020000 01ffff 010006 010005 010004 010003 010000 00ffff 000006 000005 000004 000003 000002 000001 000000 lh28f320s3-l/s3h-l 3.5 read identifier codes operation the read identifier codes operation outputs the manufacture code, device code, block status codes for each block (see fig. 2 ). using the manufacture and device codes, the system cpu can automatically match the device with its proper algorithms. the block status codes identify locked or unlocked block setting and erase completed or erase uncompleted condition. fig. 2 device identifier code memory map 3.6 query operation the query operation outputs the query structure. query database is stored in the 48-byte rom. query structure allows system software to gain critical information for controlling the flash component. query structures are always presented on the lowest-order data output (dq 0 -dq 7 ) only. 3.7 write writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when v cc = v cc1/2 and v pp = v pph1/2/3 , the cui additionally controls block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the word/byte write command requires the command and address of the location to be written. set block lock-bit command requires the command and block address within the device (block lock) to be locked. the clear block lock- bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. fig. 17 and fig. 18 illustrate we# and ce#-controlled write operations. 4 command definitions when the v pp voltage v pplk , read operations from the status register, identifier codes, query, or blocks are enabled. placing v pph1/2/3 on v pp enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 3 defines these commands.
- 11 - preliminary lh28f320s3-l/s3h-l table 2.1 bus operations (byte# = v ih ) table 2.2 bus operations (byte# = v il) mode note rp# ce 0 #ce 1 # oe# we# address v pp dq 0-15 sts read 1, 2, 3, 9 v ih v il v il v il v ih xxd out x output disable 3 v ih v il v il v ih v ih x x high z x v ih v ih standby 3 v ih v ih v il x x x x high z x v il v ih deep power-down 4 v il x x x x x x high z high z read identifier codes 9v ih v il v il v il v ih see fig. 2 x (note 5) high z query 9 v ih v il v il v il v ih see table x (note 6) high z 6 through 10 write 3, 7, 8, 9 v ih v il v il v ih v il xxd in x notes : 1. refer to section 6.2.3 "dc characteristics" . when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2/3 for v pp . see section 6.2.3 "dc characteristics" for v pplk and v pph1/2/3 voltages. 3. sts is v ol (if configured to ry/by# mode) when the wsm is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. it is floated during when the wsm is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or deep power-down mode. 4. rp# at gnd0.2 v ensures the lowest deep power- down current. 5. see section 4.2 for read identifier code data. 6. see section 4.5 for query data. 7. command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when v pp = v pph1/2/3 and v cc = v cc1/2 . 8. refer to table 3 for valid d in during a write operation. 9. dont use the timing both oe# and we# are v il . mode note rp# ce 0 #ce 1 # oe# we# address v pp dq 0-7 sts read 1, 2, 3, 9 v ih v il v il v il v ih xxd out x output disable 3 v ih v il v il v ih v ih x x high z x v ih v ih standby 3 v ih v ih v il x x x x high z x v il v ih deep power-down 4 v il x x x x x x high z high z read identifier codes 9v ih v il v il v il v ih see fig. 2 x (note 5) high z query 9 v ih v il v il v il v ih see table x (note 6) high z 6 through 10 write 3, 7, 8, 9 v ih v il v il v ih v il xxd in x
preliminary lh28f320s3-l/s3h-l - 12 - command bus cycles note first bus cycle second bus cycle req d. oper (note 1) addr (note 2) data (note 3) oper (note 1) addr (note 2) data (note 3) read array/reset 1 write x ffh read identifier codes 3 2 4 write x 90h read ia id query 3 2 write x 98h read qa qd read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase setup/confirm 2 5 write ba 20h write ba d0h full chip erase setup/confirm 2 write x 30h write x d0h word/byte write setup/write 2 5, 6 write wa 40h write wa wd alternate word/byte write 2 5, 6 write wa 10h write wa wd setup/write multi word/byte write 3 4 9 write wa e8h write wa n C 1 setup/confirm block erase and (multi) 1 5 write x b0h word/byte write suspend confirm and block erase and 1 5 write x d0h (multi) word/byte write resume block lock-bit set 2 7 write ba 60h write ba 01h setup/confirm block lock-bit reset 2 8 write x 60h write x d0h setup/confirm sts configuration level-mode for erase 2 write x b8h write x 00h and write (ry/by# mode) sts configuration 2 write x b8h write x 01h pulse-mode for erase sts configuration 2 write x b8h write x 02h pulse-mode for write sts configuration pulse-mode 2 write x b8h write x 03h for erase and write table 3 command definitions (note 10) notes : 1. b us operations are defined in table 2.1 and table 2.2 . 2. x = any valid address within the device. ia = identifier code address : see fig. 2 . qa = query offset address. ba = address within the block being erased or locked. wa = address of memory location to be written. 3. srd = data read from status register. see table 13.1 for a description of the status register bits. wd = data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id = data read from identifier codes. qd = data read from query database. 4. following the read identifier codes command, read operations access manufacture, device and block status codes. see section 4.2 for read identifier code data. 5. if the block is locked, wp# must be at v ih to enable block erase or (multi) word/byte write operations. attempts to issue a block erase or (multi) word/byte write to a locked block while rp# is v ih . 6. either 40h or 10h is recognized by the wsm as the byte write setup. 7. a block lock-bit can be set while wp# is v ih . 8. wp# must be at v ih to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. 9. following the third bus cycle, inputs the write address and write data of "n" times. finally, input the confirm command "d0h". 10. commands other than those shown above are reserved by sharp for future device implementations and should not be used.
- 13 - preliminary lh28f320s3-l/s3h-l 4.1 read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend and (multi) word/byte write suspend command. the read array command functions independently of the v pp voltage and rp# must be v ih . 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in fig. 2 retrieve the manufacture, device, block lock configuration and block erase status (see table 4 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pp voltage and rp# must be v ih . following the read identifier codes command, the following information can be read : table 4 identifier codes note : 1. x selects the specific block status code to be read. see fig. 2 for the device identifier code memory map. 4.3 read status register command the status register may be read to determine when a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration is complete and whether the operation completed successfully (see table 13.1 ). it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or ce# (either ce 0 # or ce 1 #) , whichever occurs. oe# or ce# (either ce 0 # or ce 1 #) must toggle to v ih before further reads to update the status register latch. the read status register command functions independently of the v pp voltage. rp# must be v ih . the extended status register may be read to determine multi byte write availability (see table 13.2 ). the extended status register may be read at any time by writing the multi byte write command. after writing this command, all subsequent read operations output data from the extended status register, until another valid command is written. the contents of the extended status register are latched on the falling edge of oe# or ce# (either ce 0 # or ce 1 #) , whichever occurs last in the read cycle. multi byte write command must be re-issued to update the extended status register latch. 4.4 clear status register command status register bits sr.5, sr.4, sr.3 and sr.1 are set to "1"s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 13.1 ). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register code address data manufacture code 000000h b0 000001h device code 000002h d4 000003h block status code x0004h (note 1) x0005h (note 1) ? block is unlocked dq 0 = 0 ? block is locked dq 0 = 1 ? last erase operation dq 1 = 0 completed successfully ? last erase operation did dq 1 = 1 not completed successfully ? reserved for future use dq 2-7
- 14 - preliminary lh28f320s3-l/s3h-l may be polled to determine if an error occurs during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v pp voltage. rp# must be v ih . this command is not functional during block erase, full chip erase, (multi) word/byte write, block lock-bit configuration, block erase suspend or (multi) word/byte write suspend modes. 4.5 query command query database can be read by writing query command (98h). following the command write, read cycle from address shown in table 6 through table 10 retrieve the critical information to write, erase and otherwise control the flash component. a 0 of query offset address is ignored when x8 mode (byte# = v il ). query data are always presented on the low-byte data output (dq 0 -dq 7 ). in x16 mode, high-byte (dq 8 -dq 15 ) outputs 00h. the bytes not assigned to any information or reserved for future use are set to "0". this command functions independently of the v pp voltage. rp# must be v ih . table 5 example of query structure output 4.5.1 block status register this field provides lock configuration and erase status for the specified block. these informations are only available when device is ready (sr.7 = 1). if block erase or full chip erase operation is finished irregularly, block erase status bit will be set to "1". if bit 1 is "1", this block is invalid. mode offset address output dq 15-8 dq 7-0 a 5 , a 4 , a 3 , a 2 , a 1 , a 0 1, 0, 0, 0, 0, 0 (20h) high z "q" x8 mode 1, 0, 0, 0, 0, 1 (21h) high z "q" 1, 0, 0, 0, 1, 0 (22h) high z "r" 1, 0, 0, 0, 1, 1 (23h) high z "r" a 5 , a 4 , a 3 , a 2 , a 1 x16 mode 1 , 0 , 0 , 0 , 0 (10h) 00h "q" 1 , 0 , 0 , 0 , 1 (11h) 00h "r" note : 1. ba = the beginning of a block address. table 6 query block status register offset length description (word address) (ba+2)h 01h block status register bit0 block lock configuration 0 = block is unlocked 1 = block is locked bit1 block erase status 0 = last erase operation completed successfully 1 = last erase operation not completed successfully bit2-7 reserved for future use
preliminary lh28f320s3-l/s3h-l 4.5.2 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. additionally, it indicates which version of the spec and which vendor-specified command set(s) is(are) supported. table 7 cfi query identification string offset length description (word address) 10h, 11h, 12h 03h query unique ascii string "qry" 51h, 52h, 59h 13h, 14h 02h primary vendor command set and control interface id code 01h, 00h (scs id code) 15h, 16h 02h address for primary algorithm extended query table 31h, 00h (scs extended query table offset) 17h, 18h 02h alternate vendor command set and control interface id code 0000h (0000h means that no alternate exists) 19h, 1ah 02h address for alternate algorithm extended query table 0000h (0000h means that no alternate exists) table 8 system information string offset length description (word address) 1bh 01h v cc logic supply minimum write/erase voltage 27h (2.7 v) 1ch 01h v cc logic supply maximum write/erase voltage 36h (3.6 v) 1dh 01h v pp programming supply minimum write/erase voltage 27h (2.7 v) 1eh 01h v pp programming supply maximum write/erase voltage 55h (5.5 v) 1fh 01h typical time-out per single byte/word write 03h (2 4 = 16 s) 20h 01h typical time-out for maximum size buffer write (32 bytes) 06h (2 6 = 64 s) 21h 01h typical time-out per individual block erase 09h (09h = 9, 2 9 = 512 ms) 22h 01h typical time-out for full chip erase 0fh (0fh = 15, 2 15 = 32 768 ms) 23h 01h maximum time-out per single byte/word write, 2 n times of typical. 04h (2 4 = 16, 16 s x 16 = 256 s) 24h 01h maximum time-out per maximum size buffer write, 2 n times of typical. 04h (2 4 = 16, 64 s x 16 = 1 024 s) 25h 01h maximum time-out per individual block erase, 2 n times of typical. 04h (2 4 = 16, 1 024 ms x 16 = 16 384 ms) 26h 01h maximum time-out for full chip erase, 2 n times of typical. 04h (2 4 = 16, 32 768 ms x 16 = 524 288 ms) 4.5.3 system interface information the following device information can be useful in optimizing system interface software. - 15 -
- 16 - preliminary lh28f320s3-l/s3h-l 4.5.4 device geometry definition this field provides critical details of the flash device geometry. table 9 device geometry definition offset length description (word address) 27h 01h device size 16h (16h = 22, 2 22 = 4 194 304 = 4 m bytes) 28h, 29h 02h flash device interface description 02h, 00h (x8/x16 supports x8 and x16 via byte#) 2ah, 2bh 02h maximum number of bytes in multi word/byte write 05h, 00h (2 5 = 32 bytes ) 2ch 01h number of erase block regions within device 01h (symmetrically blocked) 2dh, 2eh 02h the number of erase blocks 3fh, 00h (3fh = 63 t 63 + 1 = 64 blocks) 2fh, 30h 02h the number of "256 bytes" cluster in a erase block 00h, 01h (0100h = 256 t 256 bytes x 256 = 64 k bytes in a erase block)
preliminary lh28f320s3-l/s3h-l 4.5.5 scs oem specific extended query table certain flash features and commands may be optional in a vendor-specific algorithm specification. the optional vendor-specific query table(s) may be used to specify this and other types of information. these structures are defined solely by the flash vendor(s). table 10 scs oem specific extended query table offset length description (word address) 31h, 32h, 33h 03h pri 50h, 52h, 49h 34h 01h 31h (1) major version number , ascii 35h 01h 30h (0) minor version number, ascii 36h, 37h, 04h 0fh, 00h, 00h, 00h 38h, 39h optional command support bit0 = 1 : chip erase supported bit1 = 1 : suspend erase supported bit2 = 1 : suspend write supported bit3 = 1 : lock/unlock supported bit4 = 0 : queued erase not supported bit5-31 = 0 : reserved for future use 3ah 01h 01h supported functions after suspend bit0 = 1 : write supported after erase suspend bit1-7 = 0 : reserved for future use 3bh, 3ch 02h 03h, 00h block status register mask bit0 = 1 : block status register lock bit [bsr.0] active bit1 = 1 : block status register valid bit [bsr.1] active bit2-15 = 0 : reserved for future use 3dh 01h v cc logic supply optimum write/erase voltage (highest performance) 33h (3.3 v) 3eh 01h v pp programming supply optimum write/erase voltage (highest performance) 50h (5.0 v) 3fh reserved reserved for future versions of the scs specification - 17 -
- 18 - preliminary lh28f320s3-l/s3h-l 4.6 block erase command block erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by a block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see fig. 3 ). the cpu can detect block erase completion by analyzing the output data of the sts pin or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable block erasure can only occur when v cc = v cc1/2 and v pp = v pph1/2/3 . in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". successful block erase requires that the corresponding block lock-bit be cleared or if set, that wp# = v ih . if block erase is attempted when the corresponding block lock-bit is set and wp# = v il , sr.1 and sr.5 will be set to "1". 4.7 full chip erase command this command followed by a confirm command (d0h) erases all of the unlocked blocks. a full chip erase setup is first written, followed by a full chip erase confirm. after a confirm command is written, device erases the all unlocked blocks from block 0 to block 63 block by block. this command sequence requires appropriate sequencing. block preconditioning, erase and verify are handled internally by the wsm (invisible to the system). after the two-cycle full chip erase sequence is written, the device automatically outputs status register data when read (see fig. 4 ). the cpu can detect full chip erase completion by analyzing the output data of the sts pin or status register bit sr.7. when the full chip erase is complete, status register bit sr.5 should be checked. if erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. if error is detected on a block during full chip erase operation, wsm stops erasing the block and begin to erase the next block. reading the block valid status by issuing read id codes command or query command informs which blocks failed to its erase. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid full chip erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable full chip erasure can only occur when v cc = v cc1/2 and v pp = v pph1/2/3 . in the absence of this high voltage, block contents are protected against erasure. if full chip erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". when wp# = v ih , all blocks are erased independent of block lock-bits status. when wp# = v il , only unlocked blocks are erased. full chip erase can not be suspended.
- 19 - preliminary 4.8 word/byte write command word/byte write is executed by a two-cycle command sequence. word/byte write setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the word/byte write and write verify algorithms internally. after the word/byte write sequence is written, the device automatically outputs status register data when read (see fig. 5 ). the cpu can detect the completion of the word/byte write event by analyzing the sts pin or status register bit sr.7. when word/byte write is complete, status register bit sr.4 should be checked. if word/byte write error is detected, the status register should be cleared. the internal wsm verify only detects errors for "1"s that do not successfully write to "0"s. the cui remains in read status register mode until it receives another command. reliable word/byte writes can only occur when v cc = v cc1/2 and v pp = v pph1/2/3 . in the absence of this high voltage, memory contents are protected against word/byte writes. if word/byte write is attempted while v pp v pplk , status register bits sr.3 and sr.4 will be set to "1". successful word/byte write requires that the corresponding block lock-bit be cleared or, if set, that wp# = v ih . if word/byte write is attempted when the corresponding block lock-bit is set and wp# = v il , sr.1 and sr.4 will be set to "1". word/byte write operations with v il < wp# < v ih produce spurious results and should not be attempted. 4.9 multi word/byte write command multi word/byte write is executed by at least four- cycle or up to 35-cycle command sequence. up to 32 bytes in x8 mode (16 words in x16 mode) can be loaded into the buffer and written to the flash array. first, multi word/byte write setup (e8h) is written with the write address. at this point, the device automatically outputs extended status register data (xsr) when read (see fig. 6 and fig. 7 ). if extended status register bit xsr.7 is 0, no multi word/byte write command is available and multi word/byte write setup which just has been written is ignored. to retry, continue monitoring xsr.7 by writing multi word/byte write setup with write address until xsr.7 transitions to "1". when xsr.7 transitions to "1", the device is ready for loading the data to the buffer. a word/byte count (n)-1 is written with write address. after writing a word/byte count (n)-1 , the device automatically turns back to output status register data. the word/byte count (n)-1 must be less than or equal to 1fh in x8 mode (0fh in x16 mode). on the next write, device start address is written with buffer data. subsequent writes provide additional device address and data, depending on the count. all subsequent address must lie within the start address plus the count. after the final buffer data is written, write confirm (d0h) must be written. this initiates wsm to begin copying the buffer data to the flash array. an invalid multi word/byte write command sequence will result in both status register bits sr.4 and sr.5 being set to "1". for additional multi word/byte write, write another multi word/byte write setup and check xsr.7. the multi word/byte write command can be queued while wsm is busy as long as xsr.7 indicates "1", because lh28f320s3-l/s3h-l have two buffers. if an error occurs while writing, the device will stop writing and flush next multi word/byte write command loaded in multi word/byte write command. status register bit sr.4 will be set to "1". no multi word/byte write command is available if either sr.4 or sr.5 is set to "1". sr.4 and sr.5 should be cleared before issuing multi word/byte write command. if a multi word/byte write command is attempted past an erase block boundary, the device will write the data to flash array up to an erase block boundary and then stop writing. status register bits sr.4 and sr.5 will be set to "1". lh28f320s3-l/s3h-l
- 20 - preliminary lh28f320s3-l/s3h-l reliable multi byte writes can only occur when v cc = v cc1/2 and v pp = v pph1/2/3 . in the absence of this high voltage, memory contents are protected against multi word/byte writes. if multi word/byte write is attempted while v pp v pplk , status register bits sr.3 and sr.4 will be set to "1". successful multi word/byte write requires that the corresponding block lock-bit be cleared or, if set, that wp# = v ih . if multi byte write is attempted when the corresponding block lock-bit is set and wp# = v il , sr.1 and sr.4 will be set to "1". 4.10 block erase suspend command the block erase suspend command allows block erase interruption to read or (multi) word/byte write data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bits sr.7 and sr.6 can determine when the block erase operation has been suspended (both will be set to "1"). sts will also transition to high z. specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. a (multi) word/byte write command sequence can also be issued during erase suspend to program data in other blocks. using the (multi) word/byte write suspend command (see section 4.11 ), a (multi) word/byte write operation can also be suspended. during a (multi) word/byte write operation with block erase suspended, status register bit sr.7 will return to "0" and the sts (if set to ry/by#) output will transition to v ol . however, sr.6 will remain "1" to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and sts will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read (see fig. 8 ). v pp must remain at v pph1/2/3 (the same v pp level used for block erase) while block erase is suspended. rp# must also remain at v ih . block erase cannot resume until (multi) word/byte write operations initiated during block erase suspend have completed. 4.11 (multi) word/byte write suspend command the (multi) word/byte write suspend command allows (multi) word/byte write interruption to read data in other flash memory locations. once the (multi) word/byte write process starts, writing the (multi) word/byte write suspend command requests that the wsm suspend the (multi) word/byte write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the (multi) word/byte write suspend command is written. polling status register bits sr.7 and sr.2 can determine when the (multi) word/byte write operation has been suspended (both will be set to "1"). sts will also transition to high z. specification t whrh1 defines the (multi) word/byte write suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while (multi) word/byte write is suspended are read status register and (multi) word/byte write resume. after (multi) word/byte write resume command is written to the flash memory, the wsm will continue the (multi) word/byte write process. status register bits sr.2
- 21 - preliminary and sr.7 will automatically clear and sts will return to v ol . after the (multi) word/byte write command is written, the device automatically outputs status register data when read (see fig. 9 ). v pp must remain at v pph1/2/3 (the same v pp level used for (multi) word/byte write) while in (multi) word/byte write suspend mode. wp# must also remain at v ih or v il . 4.12 set block lock-bit command a flexible block locking and unlocking scheme is enabled via block lock-bits. the block lock-bits gate program and erase operations. with wp# = v ih , individual block lock-bits can be set using the set block lock-bit command. see table 12 for a summary of hardware and software write protection options. set block lock-bit is executed by a two-cycle command sequence. the set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). the wsm then controls the set block lock- bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see fig. 10 ). the cpu can detect the completion of the set block lock-bit event by analyzing the sts pin output or status register bit sr.7. when the set block lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally set. an invalid set block lock-bit command will result in status register bits sr.4 and sr.5 being set to "1". also, reliable operations occur only when v cc = v cc1/2 and v pp = v pph1/2/3 . in the absence of this high voltage, block lock-bit contents are protected against alteration. a successful set block lock-bit operation requires wp# = v ih . if it is attempted with wp# = v il , sr.1 and sr.4 will be set to "1" and the operation will fail. set block lock-bit operations with wp# < v ih produce spurious results and should not be attempted. 4.13 clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. with wp# = v ih , block lock-bits can be cleared using only the clear block lock-bits command. see table 12 for a summary of hardware and software write protection options. clear block lock-bits operation is executed by a two-cycle command sequence. a clear block lock- bits setup is first written. after the command is written, the device automatically outputs status register data when read (see fig. 11 ). the cpu can detect completion of the clear block lock-bits event by analyzing the sts pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bits error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock- bits command sequence will result in status register bits sr.4 and sr.5 being set to "1". also, a reliable clear block lock-bits operation can only occur when v cc = v cc1/2 and v pp = v pph1/2/3 . if a clear block lock-bits operation is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". in the absence of this high voltage, the block lock-bit contents are lh28f320s3-l/s3h-l
- 22 - preliminary lh28f320s3-l/s3h-l protected against alteration. a successful clear block lock-bits operation requires wp# = v ih . if it is attempted with wp# = v il , sr.1 and sr.5 will be set to "1" and the operation will fail. clear block lock-bits operation with v ih < rp# produce spurious results and should not be attempted. if a clear block lock-bits operation is aborted due to v pp or v cc transition out of valid range or rp# active transition, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. 4.14 sts configuration command the status (sts) pin can be configured to different states using the sts configuration command. once the sts pin has been configured, it remains in that configuration until another configuration command is issued, the device is powered down or rp# is set to v il . upon initial device power-up and after exit from deep power-down mode, the sts pin defaults to ry/by# operation where sts low indicates that the wsm is busy. sts high z indicates that the wsm is ready for a new operation. to reconfigure the sts pin to other modes, the sts configuration is issued followed by the appropriate configuration code. the three alternate configurations are all pulse mode for use as a system interrupt. the sts configuration command functions independently of the v pp voltage and rp# must be v ih . table 11 sts configuration coding description table 12 write protection alternatives operation block wp# effect lock-bit block erase or 0 v il or v ih block erase and (multi) word/byte write enabled (multi) word/byte 1 v il block is locked. block erase and (multi) word/byte write disabled write v ih block lock-bit override. block erase and (multi) word/byte write enabled full chip erase 0, 1 v il all unlocked blocks are erased, locked blocks are not erased xv ih all blocks are erased set block lock-bit x v il set block lock-bit disabled v ih set block lock-bit enabled clear block lock-bits x v il clear block lock-bits disabled v ih clear block lock-bits enabled configuration effects bits 00h set sts pin to default level mode (ry/by#). ry/by# in the default level-mode of operation will indicate wsm status condition. set sts pin to pulsed output signal for specific erase operation. in this mode, sts provides low pulse at the completion of block erase, full chip erase and clear block lock-bits operations. set sts pin to pulsed output signal for a specific write operation. in this mode, sts provides low pulse at the completion of (multi) byte write and set block lock-bit operation. set sts pin to pulsed output signal for specific write and erase operation. sts provides low pulse at the completion of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. 01h 02h 03h
preliminary lh28f320s3-l/s3h-l - 23 - table 13.1 status register definition wsms bess ecblbs wsblbs vpps wss dps r 76543210 table 13.2 extended status register definition smsrrrrrrr 76543210 xsr.7 = state machine status (sms) 1 = multi word/byte write available 0 = multi word/byte write not available xsr.6-0 = reserved for future enhancements (r) notes : after issue a multi word/byte write command : xsr.7 indicates that a next multi word/byte write command is available. xsr.6-0 are reserved for future use and should be masked out when polling the extended status register. sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear block lock-bits status (ecblbs) 1 = error in erase or clear block lock-bits 0 = successful erase or clear block lock-bits sr.4 = write and set block lock-bit status (wsblbs) 1 = error in write or set block lock-bit 0 = successful write or set block lock-bit sr.3 = v pp status (vpps) 1= v pp low detect, operation abort 0= v pp ok sr.2 = write suspend status (wss) 1 = write suspended 0 = write in progress/completed sr.1 = device protect status (dps) 1 = block lock-bit and/or wp# lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements (r) notes : check sts or sr.7 to determine block erase, full chip erase, (multi) word/byte write or block lock-bit configuration completion. sr.6-0 are invalid while sr.7 = "0". if both sr.5 and sr.4 are "1"s after a block erase, full chip erase, (multi) word/byte write, block lock-bit configuration or sts configuration attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. sr.3 is not guaranteed to reports accurate feedback only when v pp v pph1/2/3 . sr.1 does not provide a continuous indication of block lock-bit values. the wsm interrogates block lock-bit, and wp# only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set and/or wp# is not v ih . reading the block lock configuration codes after writing the read identifier codes command indicates block lock-bit status. sr.0 is reserved for future use and should be masked out when polling the status register.
preliminary lh28f320s3-l/s3h-l - 24 - block erase complete start write 70h read status register 0 0 yes no sr.7 = 1 sr.7 = 1 write 20h, block address write d0h, block address suspend block erase loop read status register full status check if desired sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command comments standby standby check sr.1 1 = device protect detect wp# = v il , block lock-bit is set only required for systems implement- ing block lock-bit configuration check sr.5 1 = block erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. block erase successful repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last block erase operation to place device in read array mode. sr.4, 5 = command sequence error 1 0 sr.5 = block erase error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4, 5 both 1 = command sequence error bus operation write read standby standby command read status register comments data = 70h addr = x status register data status register data check sr.7 1 = wsm ready 0 = wsm busy check sr.7 1 = wsm ready 0 = wsm busy erase confirm erase setup write write read data = d0h addr = within block to be erased data = 20h addr = within block to be erased suspend block erase fig. 3 automated block erase flowchart
preliminary lh28f320s3-l/s3h-l - 25 - full chip erase complete start write 70h read status register 0 0 sr.7 = 1 sr.7 = 1 write 30h write d0h read status register full status check if desired sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.4, 5 = command sequence error 1 0 bus operation command comments standby check sr.5 1 = full chip erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. full chip erase successful full status check can be done after each full chip erase. write ffh after the last full chip erase operation to place device in read array mode. sr.5 = full chip erase error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4, 5 both 1 = command sequence error bus operation write read standby standby command read status register comments data = 70h addr = x status register data status register data check sr.7 1 = wsm ready 0 = wsm busy check sr.7 1 = wsm ready 0 = wsm busy full chip erase confirm full chip erase setup write write read data = d0h addr = x data = 30h addr = x fig. 4 automated full chip erase flowchart
preliminary lh28f320s3-l/s3h-l - 26 - word/byte write complete start write 70h read status register 0 0 yes no sr.7 = 1 sr.7 = 1 write 40h or 10h, address write word/byte data and address suspend word/byte write loop read status register full status check if desired bus operation command comments standby check sr.1 1 = device protect detect wp# = v il , block lock-bit is set only required for systems implement- ing block lock-bit configuration sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. repeat for subsequent word/byte writes. sr full status check can be done after each word/byte write or after a sequence of word/byte writes. write ffh after the last word/byte write operation to place device in read array mode. standby check sr.3 1 = v pp error detect standby check sr.4 1 = data write error bus operation write read standby standby command read status register comments data = 70h addr = x status register data status register data check sr.7 1 = wsm ready 0 = wsm busy check sr.7 1 = wsm ready 0 = wsm busy word/byte write setup word/ byte write write write read data = data to be written addr = location to be written data = 40h or 10h addr = location to be written sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 word/byte write successful sr.4 = word/byte write error 1 0 suspend word/byte write fig. 5 automated word/byte write flowchart
preliminary lh28f320s3-l/s3h-l - 27 - start write e8h, start address read status register 0 xsr.7 = 1 write word or byte count (n) _ 1, start address write buffer data, start address x = 0 write buffer data, device address notes : 1. byte or word count values on dq 0-7 are loaded into the count register. 2. write buffer contents will be programmed at the start address. 3. align the start address on a write buffer boundary for maximum programming performance. 4. the device aborts the multi word/byte write command if the current address is outside of the original block address. 5. the status register indicates an "improper command sequence" if the multi word/byte write command is aborted. follow this with a clear status register command. sr full status check can be done after each multi word/byte write or after a sequence of multi word/byte writes. write ffh after the last multi word/byte write operation to place device in read array mode. bus operation write read standby write (note 1) command setup multi word/byte write comments data = e8h addr = start address data = word or byte count (n) _ 1 addr = start address write (note 2, 3) data = buffer data addr = start address write (note 4, 5) data = buffer data addr = device address write data = d0h addr = x read status register data standby extended status register data check sr.7 1 = wsm ready 0 = wsm busy multi word/byte write abort yes no no x = n no write buffer time-out yes full status check if desired sr.7 = multi word/byte write complete 0 1 x = x + 1 write d0h read status register yes no yes no suspend multi word/byte write loop write another block address check xsr.7 1 = multi word/byte write ready 0 = multi word/byte write busy yes abort buffer write command? another buffer write ? suspend multi word/byte write fig. 6 automated multi word/byte write flowchart
preliminary lh28f320s3-l/s3h-l - 28 - sr.3 = full status check procedure for multi word/byte write operation read status register v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command standby check sr.1 1 = device protect detect wp# = v il , block lock-bit is set only required for systems implement- ing block lock-bit configuration sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. sr.4, 5 = command sequence error 1 0 multi word/byte write successful sr.4 = multi word/byte write error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4, 5 both 1 = command sequence error standby check sr.4 1 = data write error comments fig. 7 full status check procedure for automated multi word/byte write
preliminary lh28f320s3-l/s3h-l - 29 - block erase resumed start write b0h read status register 0 sr.7 = bus operation write read standby standby command erase suspend comments data = b0h addr = x status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = block erase suspended 0 = block erase completed sr.6 = read or write? read array data (multi) word/byte write loop done? write d0h block erase completed write ffh read array data 1 1 0 no yes write erase resume data = d0h addr = x read (multi) word/byte write fig. 8 block erase suspend/resume flowchart
preliminary lh28f320s3-l/s3h-l - 30 - (multi) word/byte write resumed start write b0h read status register 0 sr.7 = 1 write ffh bus operation write read standby standby command (multi) word/ byte write suspend comments data = b0h addr = x status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = (multi) word/byte write suspended 0 = (multi) word/byte write completed read array sr.2 = read array data done reading write d0h (multi) word/byte write completed write ffh read array data 1 0 no yes write read write (multi) word/ byte write resume data = ffh addr = x read array locations other than that being written. data = d0h addr = x fig. 9 (multi) word/byte write suspend/resume flowchart
preliminary lh28f320s3-l/s3h-l - 31 - set block lock-bit complete start write 60h, block address write 01h, block address read status register 0 sr.7 = 1 full status check if desired repeat for subsequent block lock-bit set operations. full status check can be done after each block lock-bit set operation or after a sequence of block lock-bit set operations. write ffh after the last block lock-bit set operation to place device in read array mode. bus operation write write read standby command set block lock-bit setup comments data = 60h addr = block address data = 01h addr = block address status register data check sr.7 1 = wsm ready 0 = wsm busy sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command comments standby standby check sr.1 1 = device protect detect wp# = v il check sr.4 1 = set block lock-bit error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple block lock-bits are set before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. set block lock-bit confirm set block lock-bit successful sr.4, 5 = command sequence error 1 0 sr.4 = set block lock-bit error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4, 5 both 1 = command sequence error fig. 10 set block lock-bit flowchart
preliminary lh28f320s3-l/s3h-l - 32 - clear block lock-bits complete start write 60h write d0h read status register 0 sr.7 = 1 full status check if desired write ffh after the last clear block lock-bits operation to place device in read array mode. bus operation write write read standby command clear block lock-bits setup comments data = 60h addr = x data = d0h addr = x status register data check sr.7 1 = wsm ready 0 = wsm busy sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command comments standby standby check sr.1 1 = device protect detect wp# = v il check sr.5 1 = clear block lock-bits error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command. if error is detected, clear the status register before attempting retry or other error recovery. clear block lock-bits confirm clear block lock-bits successful sr.4, 5 = command sequence error 1 0 sr.5 = clear block lock-bits error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4, 5 both 1 = command sequence error fig. 11 clear block lock-bits flowchart
- 33 - preliminary 5 design consideration 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three- line control provides for : a. lowest possible memory power consumption. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the systems read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 sts and block erase, full chip erase, (multi) word/byte write and block lock-bit configuration polling sts is an open drain output that should be connected to v cc by a pullup resistor to provide a hardware method of detecting block erase, full chip erase, (multi) word/byte write and block lock-bit configuration completion. in default mode, it transitions low after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration commands and returns to v oh when the wsm has finished executing the internal algorithm. for alternate sts pin configurations, see the configu- ration command ( table 3 and section 4.14 ). sts can be connected to an interrupt input of the system cpu or controller. it is active at all times. sts, in default mode, is also high z when the device is in block erase suspend (with (multi) word/byte write inactive), (multi) word/byte write suspend or deep power-down modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 f ceramic capacitor connected between its v cc and gnd and between its v pp and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the arrays power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 v pp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. use similar trace widths and layout considerations given to the v cc power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. 5.5 v cc , v pp , rp# transitions block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if v pp falls outside of a valid v pph1/2/3 range, v cc falls outside of a valid v cc1/2 range, or rp# = v il . if v pp error is detected, status register bit sr.3 is set to "1" along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v il during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, sts (if set to lh28f320s3-l/s3h-l
- 34 - preliminary lh28f320s3-l/s3h-l ry/by# mode) will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v il clear the status register. the cui latches commands issued by system software and is not altered by v pp or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from deep power- down or after v cc transitions below v lko . after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, even after v pp transitions down to v pplk , the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. 5.6 power-up/down protection the device is designed to offer protection against accidental block and full chip erasure, (multi) word/byte writing or block lock-bit configuration during power transitions. upon power-up, the device is indifferent as to which power supply (v pp or v cc ) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we# and ce# must be low for a command write, driving either to v ih will inhibit writes. the cuis two-step command sequence architecture provides added level of protection against data alteration. in-system block lock and unlock capability prevents inadvertent data alteration. the device is disabled while rp# = v il regardless of its control inputs state. 5.7 power consumption when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memorys nonvolatility increases usable battery life because data is retained when system power is removed. in addition, deep power-down mode ensures extremely low power consumption even when system power is applied. for example, portable computing products and other power sensitive applications that use an array of devices for solid- state storage can consume negligible power by lowering rp# to v il standby or sleep modes. if access is again needed, the devices can be read following the t phqv and t phwl wake-up cycles required after rp# is first raised to v ih. see section 6.2.4 through 6.2.6 " ac characteristics - read-only and write operations " and fig. 15 , fig. 16 , fig. 17 , and fig. 18 for more information.
- 35 - preliminary 6 electrical specifications 6.1 absolute maximum ratings * operating temperature ? lh28f320s3-l during read, erase, write and block lock-bit configuration ... 0 to +70c (note 1) temperature under bias ............. C10 to +80c ? LH28F320S3H-L during read, erase, write and block lock-bit configuration .... C 40 to +85c (note 2) temperature under bias ............. C 40 to +85c storage temperature ........................ C 65 to +125c voltage on any pin (except v cc , v pp ) .... C 0.5 v to v cc +0.5 v (note 3) v cc supply voltage ................. C 0.2 to +7.0 v (note 3) v pp update voltage during erase, write and block lock-bit configuration .. C 0.2 to +7.0 v (note 3) output short circuit current .............. 100 ma (note 4) * warning : stressing the device beyond the " absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes : 1. operating temperature is for commercial product defined by this specification. 2. operating temperature is for extended temperature product defined by this specification. 3. all specified voltages are with respect to gnd. minimum dc voltage is C 0.5 v on input/output pins and C 0.2 v on v cc and v pp pins. during transitions, this level may undershoot to C 2.0 v for periods < 20 ns. maximum dc voltage on input/output pins and v cc is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods < 20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. notice : the specifications are subject to change without notice. verify with your local sharp sales office that you have the latest datasheet before finalizing a design. lh28f320s3-l/s3h-l symbol parameter note min. max. unit versions t a operating temperature 1 0 +70 ? c lh28f320s3-l C40 +85 ?c LH28F320S3H-L v cc1 v cc supply voltage (2.7 to 3.6 v) 2.7 3.6 v v cc2 v cc supply voltage (3.30.3 v) 3.0 3.6 v 6.2 operating conditions note : 1. test condition : ambient temperature note : 1. sampled, not 100% tested. symbol parameter typ. max. unit condition c in input capacitance 7 10 pf v in = 0.0 v c out output capacitance 9 12 pf v out = 0.0 v 6.2.1 capacitance (note 1) t a = +25 ? c, f = 1 mhz
preliminary lh28f320s3-l/s3h-l - 36 - 6.2.2 ac input/output test conditions test points input output 1.35 1.35 2.7 0.0 fig. 12 transient input/output reference waveform for v cc = 2.7 to 3.6 v 1.5 1.5 3.0 0.0 test points input output fig. 13 transient input/output reference waveform for v cc = 3.3 0.3 v ac test inputs are driven at 2.7 v for a logic "1" and 0.0 v for a logic "0". input timing begins, and output timing ends, at 1.35 v. input rise and fall times (10% to 90%) < 10 ns. ac test inputs are driven at 3.0 v for a logic "1" and 0.0 v for a logic "0". input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) < 10 ns. fig. 14 transient equivalent testing load circuit device under test c l includes jig capacitance r l = 3.3 k w c l out 1.3 v 1n914 test configuration c l (pf) v cc = 3.30.3 v, 2.7 to 3.6 v 50 test configuration capacitance loading value
preliminary lh28f320s3-l/s3h-l - 37 - 6.2.3 dc characteristics symbol parameter note v cc = 2.7 to 3.6 v v cc = 3.30.3 v unit test typ. max. typ. max. conditions i li input load current 1 0.5 0.5 a v cc = v cc max. v in = v cc or gnd i lo output leakage current 1 0.5 0.5 a v cc = v cc max. v out = v cc or gnd cmos inputs 20 100 20 100 a v cc = v cc max. i ccs v cc standby current 1, 3, 6 ce# = rp# = v cc 0.2 v ttl inputs 1414mav cc = v cc max. ce# = rp# = v ih i ccd v cc deep power- lh28f320s3-l 1 20 20 a rp# = gnd0.2 v down current LH28F320S3H-L 25 25 i out (sts) = 0 ma cmos inputs 30 30 ma v cc = v cc max. ce# = gnd i ccr v cc read current 1, 5, 6 f = 5 mhz, i out = 0 ma ttl inputs 35 35 ma v cc = v cc max. ce# = v il f = 5 mhz, i out = 0 ma v cc write current 17 ma v pp = 2.7 to 3.6 v i ccw ((multi) w/b write or 1, 7 17 17 ma v pp = 3.30.3 v set block lock-bit) 17 17 ma v pp = 5.00.5 v v cc erase current 17 ma v pp = 2.7 to 3.6 v i cce (block erase, full chip erase, 1, 7 17 17 ma v pp = 3.30.3 v clear block lock-bits) 17 17 ma v pp = 5.00.5 v i ccws v cc write or block erase 1, 2 1 6 1 6 ma ce# = v ih i cces suspend current i pps v pp standby current 1 2 15 2 15 a v pp v cc i ppr v pp read current 1 10 200 10 200 a v pp > v cc i ppd v pp deep power-down 1 0.1 5 0.1 5 a rp# = gnd0.2 v current v pp write current 80 ma v pp = 2.7 to 3.6 v i ppw ((multi) w/b write or 1, 7 80 80 ma v pp = 3.30.3 v set block lock-bit) 80 80 ma v pp = 5.00.5 v v pp erase current 40 ma v pp = 2.7 to 3.6 v i ppe (block erase, full chip erase, 1, 7 40 40 ma v pp = 3.30.3 v clear block lock-bits) 40 40 ma v pp = 5.00.5 v i ppws v pp write or block erase 1 10 200 10 200 a v pp = v pph1/2/3 i ppes suspend current
preliminary lh28f320s3-l/s3h-l - 38 - 6.2.3 dc characteristics (contd.) notes : 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a = +25c. these currents are valid for all product versions (packages and speeds). 2. i ccws and i cces are specified with the device de- selected. if reading or (multi) word/byte writing in erase suspend mode, the devices current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 3. includes sts. 4. block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph1 (min.) , between v pph1 (max.) and v pph2 (min.), between v pph2 (max.) and v pph3 (min) and above v pph3 (max). 5. automatic power saving (aps) reduces typical i ccr to 3 ma at 2.7 v and 3.3 v v cc in static operation. 6. cmos inputs are either v cc 0.2 v or gnd0.2 v. ttl inputs are either v il or v ih . 7. sampled, not 100% tested. symbol parameter note v cc = 2.7 to 3.6 v v cc = 3.30.3 v unit test min. max. min. max. conditions v il input low voltage 7 C 0.5 0.8 C 0.5 0.8 v v ih input high voltage 7 2.0 v cc 2.0 v cc v +0.5 +0.5 v ol output low voltage 3, 7 0.4 0.4 v v cc = v cc min. i ol = 2 ma v oh1 output high voltage 3, 7 2.4 2.4 v v cc = v cc min. (ttl) i oh = C2.5 ma 0.85 0.85 v v cc = v cc min. v oh2 output high voltage 3, 7 v cc v cc i oh = C2.5 ma (cmos) v cc v cc v v cc = v cc min. C 0.4 C 0.4 i oh = C100 a v pplk v pp lockout voltage 4, 7 1.5 1.5 v during normal operations v pph1 v pp voltage during write 2.7 3.6 v or erase operations v pph2 v pp voltage during write 3.0 3.6 3.0 3.6 v or erase operations v pph3 v pp voltage during write 4.5 5.5 4.5 5.5 v or erase operations v lko v cc lockout voltage 2.0 2.0 v
preliminary lh28f320s3-l/s3h-l - 39 - 6.2.4 ac characteristics - read-only operations (note 1) ? v cc = 2.7 to 3.6 v, t a = 0 to +70 ? c or C 40 to +85c versions lh28f320s3-l11 lh28f320s3-l14 LH28F320S3H-L11 LH28F320S3H-L14 unit symbol parameter note min. max. min. max. t avav read cycle time 140 160 ns t avqv address to output delay 140 160 ns t elqv ce# to output delay 2 140 160 ns t phqv rp# high to output delay 600 600 ns t glqv oe# to output delay 2 50 55 ns t elqx ce# to output in low z 3 0 0 ns t ehqz ce# high to output in high z 3 50 55 ns t glqx oe# to output in low z 3 0 0 ns t ghqz oe# high to output in high z 3 20 25 ns t oh output hold from address, ce# or 30 0 ns oe# change, whichever occurs first t flqv byte# to output delay 3 140 160 ns t fhqv t flqz byte# to output in high z 3 30 40 ns t elfl ce# low to byte# high or low 3 5 5 ns t elfh versions lh28f320s3-l11 lh28f320s3-l14 LH28F320S3H-L11 LH28F320S3H-L14 unit symbol parameter note min. max. min. max. t avav read cycle time 110 140 ns t avqv address to output delay 110 140 ns t elqv ce# to output delay 2 110 140 ns t phqv rp# high to output delay 600 600 ns t glqv oe# to output delay 2 45 50 ns t elqx ce# to output in low z 3 0 0 ns t ehqz ce# high to output in high z 3 50 55 ns t glqx oe# to output in low z 3 0 0 ns t ghqz oe# high to output in high z 3 20 25 ns t oh output hold from address, ce# or 30 0 ns oe# change, whichever occurs first t flqv byte# to output delay 3 110 140 ns t fhqv t flqz byte# to output in high z 3 30 40 ns t elfl ce# low to byte# high or low 3 5 5 ns t elfh notes : 1. see ac input/output reference waveform ( fig. 12 and fig. 13 ) for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. ?v cc = 3.30.3 v, t a = 0 to +70?c or C 40 to +85c
preliminary lh28f320s3-l/s3h-l - 40 - addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# (p) v cc v il v oh v ol v ih v ih v ih v ih v ih v il v il v il v il standby device address selection data valid address stable high z valid output high z t glqv t elqv t glqx t elqx t avqv t phqv t avav t ehqz t ghqz t oh fig. 15 ac waveform for read operations note : ce# is defined as the latter of ce 0 # and ce 1 # going low or the first of ce 0 # or ce 1 # going high.
preliminary lh28f320s3-l/s3h-l - 41 - addresses (a) ce# (e) oe# (g) byte# (f) data (d/q) (dq 0 -dq 7 ) standby device address selection data valid address stable v il v oh v ol v ih v ih v ih v ih v il v il v il data (d/q) (dq 8 -dq 15 ) v oh v ol high z data output high z valid output high z high z data output t avav t ehqz t ghqz t glqv t elqv t glqx t elqx t oh t avfl = t elfl t flqv = t avqv t flqz t elfl t avqv fig. 16 byte# timing waveforms note : ce# is defined as the latter of ce 0 # and ce 1 # going low or the first of ce 0 # or ce 1 # going high.
- 42 - preliminary lh28f320s3-l/s3h-l 6.2.5 ac characteristics - write operations (note 1) ? v cc = 2.7 to 3.6 v, t a = 0 to +70 ? c or C 40 to +85c versions lh28f320s3-l11 lh28f320s3-l14 LH28F320S3H-L11 LH28F320S3H-L14 unit symbol parameter note min. max. min. max. t avav write cycle time 140 160 ns t phwl rp# high recovery to we# going low 2 1 1 s t elwl ce# setup to we# going low 10 10 ns t wlwh we# pulse width 55 55 ns t shwh wp# v ih setup to we# going high 2 100 100 ns t vpwh v pp setup to we# going high 2 100 100 ns t avwh address setup to we# going high 3 50 50 ns t dvwh data setup to we# going high 3 50 50 ns t whdx data hold from we# high 5 5 ns t whax address hold from we# high 5 5 ns t wheh ce# hold from we# high 10 10 ns t whwl we# pulse width high 30 30 ns t whrl we# high to sts going low 100 100 ns t whgl write recovery before read 0 0 ns t qvvl v pp hold from valid srd, sts high z 2, 4 0 0 ns t qvsl wp# v ih hold from valid srd, sts high z 2, 4 0 0 ns versions lh28f320s3-l11 lh28f320s3-l14 LH28F320S3H-L11 LH28F320S3H-L14 unit symbol parameter note min. max. min. max. t avav write cycle time 110 140 ns t phwl rp# high recovery to we# going low 2 1 1 s t elwl ce# setup to we# going low 10 10 ns t wlwh we# pulse width 55 55 ns t shwh wp# v ih setup to we# going high 2 100 100 ns t vpwh v pp setup to we# going high 2 100 100 ns t avwh address setup to we# going high 3 50 50 ns t dvwh data setup to we# going high 3 50 50 ns t whdx data hold from we# high 5 5 ns t whax address hold from we# high 5 5 ns t wheh ce# hold from we# high 10 10 ns t whwl we# pulse width high 30 30 ns t whrl we# high to sts going low 100 100 ns t whgl write recovery before read 0 0 ns t qvvl v pp hold from valid srd, sts high z 2, 4 0 0 ns t qvsl wp# v ih hold from valid srd, sts high z 2, 4 0 0 ns ?v cc = 3.30.3 v, t a = 0 to +70 ? c or C 40 to +85c notes : 1. read timing characteristics during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations are the same as during read- only operations. refer to section 6.2.4 "ac characteristics" for read-only operations. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in and d in for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. v pp should be held at v pph1/2/3 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (sr.1/3/4/5 = 0).
preliminary lh28f320s3-l/s3h-l - 43 - (note 1) (note 2) (note 3) (note 4) (note 5) (note 6) v il v ih high z v ih v ih v ih v il v il v il v ol v il v ih v il v pplk v pph1/2/3 v ih v il addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# (p) v pp (v) sts (r) wp# (s) v il v ih a in a in t avav t avwh t elwl t wheh t whgl t whwl t whqv1/2/3/4 t wlwh t dvwh t whdx valid srd t phwl t whrl t vpwh t qvvl d in d in high z d in t shwh t qvsl t whax fig. 17 ac waveform for we#-controlled write operations notes : 1. v cc power-up and standby. 2. write erase or write setup. 3. write erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. 7. ce# is defined as the latter of ce 0 # and ce 1 # going low or the first of ce 0 # or ce 1 # going high.
preliminary lh28f320s3-l/s3h-l - 44 - notes : 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in and d in for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. v pp should be held at v pph1/2/3 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (sr.1/3/4/5 = 0). 6.2.6 alternative ce#-controlled writes (note 1) ?v cc = 2.7 to 3.6 v, t a = 0 to +70?c or C 40 or +85c ?v cc = 3.30.3 v, t a = 0 to +70?c or C 40 to +85c versions lh28f320s3-l11 lh28f320s3-l14 LH28F320S3H-L11 LH28F320S3H-L14 unit symbol parameter note min. max. min. max. t avav write cycle time 140 160 ns t phel rp# high recovery to ce# going low 2 1 1 s t wlel we# setup to ce# going low 0 0 ns t eleh ce# pulse width 70 70 ns t sheh wp# v ih setup to ce# going high 2 100 100 ns t vpeh v pp setup to ce# going high 2 100 100 ns t aveh address setup to ce# going high 3 50 50 ns t dveh data setup to ce# going high 3 50 50 ns t ehdx data hold from ce# high 5 5 ns t ehax address hold from ce# high 5 5 ns t ehwh we# hold from ce# high 0 0 ns t ehel ce# pulse width high 25 25 ns t ehrl ce# high to sts going low 100 100 ns t ehgl write recovery before read 0 0 ns t qvvl v pp hold from valid srd, sts high z 2, 4 0 0 ns t qvsl wp# v ih hold from valid srd, sts high z 2, 4 0 0 ns versions lh28f320s3-l11 lh28f320s3-l14 LH28F320S3H-L11 LH28F320S3H-L14 unit symbol parameter note min. max. min. max. t avav write cycle time 110 140 ns t phel rp# high recovery to ce# going low 2 1 1 s t wlel we# setup to ce# going low 0 0 ns t eleh ce# pulse width 70 70 ns t sheh wp# v ih setup to ce# going high 2 100 100 ns t vpeh v pp setup to ce# going high 2 100 100 ns t aveh address setup to ce# going high 3 50 50 ns t dveh data setup to ce# going high 3 50 50 ns t ehdx data hold from ce# high 5 5 ns t ehax address hold from ce# high 5 5 ns t ehwh we# hold from ce# high 0 0 ns t ehel ce# pulse width high 25 25 ns t ehrl ce# high to sts going low 100 100 ns t ehgl write recovery before read 0 0 ns t qvvl v pp hold from valid srd, sts high z 2, 4 0 0 ns t qvsl wp# v ih hold from valid srd, sts high z 2, 4 0 0 ns
preliminary lh28f320s3-l/s3h-l - 45 - (note 1) (note 2) (note 3) (note 4) (note 5) (note 6) v il v ih high z v ih v ih v ih v il v il v il v ol v il v ih v il v pplk v pph1/2/3 v ih v il addresses (a) we# (w) oe# (g) ce# (e) data (d/q) rp# (p) v pp (v) sts (r) wp# (s) v il v ih a in a in t avav t aveh t wlel t ehwh t ehgl t ehel t ehqv1/2/3/4 t eleh t dveh t ehdx valid srd t phel t ehrl t vpeh t qvvl d in d in high z d in t sheh t qvsl t ehax fig. 18 ac waveform for ce#-controlled write operations notes : 1. v cc power-up and standby. 2. write erase or write setup. 3. write erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. 7. ce# is defined as the latter of ce 0 # and ce 1 # going low or the first of ce 0 # or ce 1 # going high.
preliminary lh28f320s3-l/s3h-l - 46 - 6.2.7 reset operations rp# (p) v il (a) reset during read array mode (b) reset during block erase, full chip erase, (multi) word/byte write v ih high z v ih high z v ol v il v ol sts (r) sts (r) rp# (p) v il v ih rp# (p) v il v cc 2.7 v/3.3 v or block lock-bit configuration (c) v cc power up timing t plph t plrh t plph t 23vph fig. 19 ac waveform for reset operation reset ac specifications (note 1) notes : 1. these specifications are valid for all product versions (packages and speeds). 2. if rp# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is not executing, the reset will complete within 100 ns. 3. a reset time, t phqv , is required from the latter of sts going high z or rp# going high until outputs are valid. 4. when the device power-up, holding rp#-low minimum 100 ns is required after v cc has been in predefined range and also has been in stable there. v cc = 2.7 to 3.6 v v cc = 3.30.3 v unit symbol parameter note min. max. min. max. t plph rp# pulse low time (if rp# is tied to v cc , 100 100 ns this specification is not applicable) rp# low to reset during block erase, t plrh full chip erase, (multi) word/byte write 2, 3 21.5 21.1 s or block lock-bit configuration t 23vph v cc 2.7 v to rp# high 4 100 100 ns v cc 3.0 v to rp# high
preliminary lh28f320s3-l/s3h-l - 47 - 6.2.8 block erase, full chip erase, (multi) word/byte write and block lock-bit configuration performance (note 3, 4) ?v cc = 2.7 to 3.6 v, t a = 0 to +70?c or C 40 to +85c notes : 1. typical values measured at t a = +25?c and nominal voltages. assumes corresponding block lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, not 100% tested. v pp = 2.7 to 3.6 v v pp = 3.30.3 v v pp = 5.00.5 v symbol parameter note min. typ. (note 1) max. min. typ. (note 1) max. min. typ. (note 1) max. unit t whqv1 word/byte write time t ehqv1 (using w/b write, 2 22.19 tbd 22.19 tbd 13.2 tbd s in word mode) t whqv1 word/byte write time t ehqv1 (using w/b write, 2 19.9 tbd 19.9 tbd 13.2 tbd s in byte mode) word/byte write time (using multi word/byte 2 5.76 tbd 5.76 tbd 2.76 tbd s write) block write time (using w/b write, 2 0.73 8.2 0.73 8.2 0.44 4.8 s in word mode) block write time (using w/b write, 2 1.31 16.5 1.31 16.5 0.87 10.9 s in byte mode) block write time (using multi word/byte 2 0.37 4.1 0.37 4.1 0.18 2 s write) t whqv2 block erase time 2 0.56 10 0.56 10 0.42 10 s t ehqv2 full chip erase time 35.9 tbd 35.9 tbd 26.9 tbd s t whqv3 set block lock-bit 2 22.17 tbd 22.17 tbd 13.2 tbd s t ehqv3 time t whqv4 clear block lock-bits 2 0.56 tbd 0.56 tbd 0.42 tbd s t ehqv4 time t whrh1 write suspend latency 7.24 10.2 7.24 10.2 6.73 9.48 s t ehrh1 time to read t whrh2 erase suspend latency 15.5 21.5 15.5 21.5 12.54 17.54 s t ehrh2 time to read
preliminary lh28f320s3-l/s3h-l - 48 - v pp = 3.30.3 v v pp = 5.00.5 v symbol parameter note min. typ. (note 1) max. min. typ. (note 1) max. unit t whqv1 word/byte write time 2 21.75 tbd 12.95 tbd s t ehqv1 (using w/b write, in word mode) t whqv1 word/byte write time 2 19.51 tbd 12.95 tbd s t ehqv1 (using w/b write, in byte mode) word/byte write time 2 5.66 tbd 2.7 tbd s (using multi word/byte write) block write time 2 0.72 8.2 0.43 4.8 s (using w/b write, in word mode) block write time 2 1.28 16.5 0.85 10.9 s (using w/b write, in byte mode) block write time 2 0.36 4.1 0.18 2 s (using multi word/byte write) t whqv2 block erase time 2 0.55 10 0.41 10 s t ehqv2 full chip erase time 35.2 tbd 26.3 tbd s t whqv3 set block lock-bit time 2 21.75 tbd 12.95 tbd s t ehqv3 t whqv4 clear block lock-bits time 2 0.55 tbd 0.41 tbd s t ehqv4 t whrh1 write suspend latency time to read 7.1 10 6.6 9.3 s t ehrh1 t whrh2 erase suspend latency time to read 15.2 21.1 12.3 17.2 s t ehrh2 notes : 1. typical values measured at t a = +25?c and nominal voltages. assumes corresponding block lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, not 100% tested. 6.2.8 block erase, full chip erase, (multi) word/byte write and block lock-bit configuration performance (contd.) (note 3, 4) ?v cc = 3.30.3 v, t a = 0 to +70?c or C 40 to +85c
preliminary 7 ordering information lh28f320s3 (h) ns - l 1 1 device density 320 = 32 m-bit access speed (ns) 11 : 110 ns (3.3 0.3 v), 140 ns (2.7 to 3.6 v) 14 : 140 ns (3.3 0.3 v), 160 ns (2.7 to 3.6 v) package ns = 56-pin ssop (ssop056-p-0600) b = 80-ball csp (fbga080/064-p-0818) architecture s = symmetrical block power supply type 3 = smart 3 technology operating temperature blank = 0 to +70 c h = 40 to +85 c product line designator for all sharp flash products valid operational combinations option order code v cc = 2.7 to 3.6 v v cc = 3.3 0.3 v 50 pf load, 50 pf load, 1.35 v i/o levels 1.5 v i/o levels 1 lh28f320s3xx-l11 140 ns 110 ns 2 lh28f320s3xx-l14 160 ns 140 ns lh28f320s3-l/s3h-l - 49 -
packaging 0.10 0.15 m 0.15 0.05 23.7 0.2 1.85 max. 0.52 0.1 0.15 (1.28) p _ 0.8 typ. package base plane (14.4) 13.3 0.2 16.0 0.3 56 _ 0.3 0.1 28 1 56 29 56 ssop (ssop056-p-0600)
packaging c d 0.4 typ. 0.8 typ. 1.4 typ. a b s 0.1 s 2.4 typ. * 0.4 typ. 0.1 s 1.2 max. 8.0 + 0.2 0 0.8 typ. 0.4 typ. 1.2 typ. h a 1 20 s m 0.30 ab scd m 0.15 18.0 + 0.2 0 0.35 0.05 0.45 0.03 * land hole diameter for ball mounting / / 80 csp (fbga080/064-p-0818)

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